The present invention relates the field of computer architecture and particularly to the field of virtual memory.
Virtual memory computer architectures have become increasingly popular in modern times. This popularity has increased to extent that even most microprocessor/personal computer systems now utilise virtual memory. Virtual memory has known significant advantages in simplifying the software production process.
In order to speed up the operation of the computer system, it has been suggested a number of co-processors could be utilised to speed up various operations such as the production of graphical images for display or printing out. It would be advantageous if such systems could operate in conjunction utilising virtual memory.
In accordance with a first aspect of the invention, there is provided a co-processor adapted for using virtual memory with a host processing device, a memory coupled to the host processing device to implement the virtual memory, the co-processor including:
virtual-physical memory mapping device for interrogating a virtual memory table and for mapping one or more virtual memory addresses requested by the co-processor into corresponding physical addresses in the memory of the host processing device.
Preferably, the virtual memory table is stored in two or more non-contiguously addressable regions of the memory, and may be a page table.
Preferably, the virtual-physical memory mapping device further includes a multiple-entry translation lookaside buffer for caching virtual-to-physical address mappings. The translation lookaside buffer is adapted to replace entries therein on a least recently used replacement basis. The virtual-physical memory mapping device may also include devices for comparing, replacing, singly invalidating and multiply invalidating one or more entries of the translation lookaside buffer. Still further, the virtual-physical memory mapping device may include a device for, upon an occurrence of a miss in the translation lookaside buffer, hashing a virtual memory address using a hash function to produce an index into the virtual memory table of the host processing device.
In accordance with a second aspect of the invention, there is provided a method of operating a co-processor to use virtual memory with a host processing device, a memory coupled to the host processing device to implement the virtual memory, the method including the steps of:
interrogating a virtual memory table; and
mapping one or more virtual memory addresses requested by the co-processor into corresponding physical addresses in the memory of the host processing device.
In accordance with a third aspect of the invention, there is provided a memory management apparatus for a co-processor coupled to a host processor with virtual memory, the virtual memory comprising a plurality of virtual-memory pages contained in a host memory coupled to the host processor, the host memory comprising a plurality of physical pages, the memory management apparatus including:
buffering device for caching a predetermined number of virtual-to-physical memory address mappings, each memory-address mapping including a virtual-memory address and a corresponding physical address;
device for comparing a virtual-memory address requested by the co-processor with the memory-address mappings currently cached by the buffering device;
device for, if the comparing device determines the virtual memory address requested by the co-processor matches a virtual-memory address of one of the memory-address mappings in the buffering device, providing a physical address to the co-processor from the matching memory-address mapping; and
device for, if the comparing device determines the virtual-memory address requested by the co-processor does not match the virtual memory address of any memory-address mapping currently cached in the buffering device, updating the buffering device with a memory-address mapping retrieved from a page table, the retrieved memory-address mapping containing a physical address corresponding to the virtual memory address requested by the co-processor, the page table stored in a predetermined number of the physical pages.
In accordance with a fourth aspect of the invention, there is provided a method of managing virtual memory for a co-processor coupled to a host processor with the virtual memory, the virtual memory comprising a plurality of virtual-memory pages contained in a host memory coupled to the host processor, the host memory comprising a plurality of physical pages, the method including the steps of:
caching a predetermined number of virtual-to-physical memory address mappings in buffering device, each memory-address mapping including a virtual-memory address and a corresponding physical address;
comparing a virtual-memory address requested by the co-processor with the memory-address mappings currently cached by the buffering device;
if the comparison determines the virtual memory address requested by the co-processor matches a virtual-memory address of one of the memory-address mappings in the buffering device, providing a physical address to the co-processor from the matching memory-address mapping; and
if the comparison determines the virtual-memory address requested by the co-processor does not match the virtual memory address of any memory-address mapping currently cached in the buffering device, updating the buffering device with a memory-address mapping retrieved from a page table, the retrieved memory-address mapping containing a physical address corresponding to the virtual memory address requested by the co-processor, the page table stored in a predetermined number of the physical pages.
In accordance with a fifth aspect of the invention, there is provided a system for managing virtual memory, the system including:
a host processing device;
a host memory coupled to the host processing device to implement the virtual memory;
a co-processor adapted for using virtual memory;
virtual-physical memory mapping device, coupled to the co-processor, for interrogating a virtual memory table and for mapping one or more virtual memory addresses requested by the co-processor into corresponding physical addresses in the host memory.
In the following detailed description, the reader""s attention is directed, in particular, to FIGS. 150 to 154 and their associated description without intending to detract from the disclosure of the remainder of the description.